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ISL59481
Data Sheet December 22, 2006 FN6208.3
Dual, 500MHz Triple, Multiplexing Amplifiers
The ISL59481 contains two independent unity gain triple 4:1 MUX amplifiers that feature high slew rate and excellent bandwidth for RGB video switching. Each RGB 4:1 MUX contains binary coded, channel select logic inputs (S0, S1), and separate logic inputs for High Impedance output (HIZ) and power-down (EN) modes. The HIZ state presents a high impedance at the output so that both RGB MUX outputs can be wired together to form an 8:1 RGB MUX amplifier or they can be used in R-R, G-G, and B-B pairs to form a 4:1 differential input/output MUX. Separate power-down mode controls (EN1, EN2) are included to turn off unused circuitry in power sensitive applications. With both EN pins pulled high, the ISL59481 enters a standby power mode consuming just 36mW.
Features
* Dual, triple 4:1 multiplexers for RGB * Externally configurable for various video MUX circuits including - 8:1 RGB MUX - Two separate 4:1 RGB MUX - 4:1 differential RGB video MUX * Internally set gain-of-1 * High impedance outputs (HIZ) * Power-down mode (EN) * 5V operation * 870V/s slew rate * 500MHz bandwidth * Supply current 16mA/CH
Ordering Information
PART NUMBER (Note) ISL59481IRZ PART MARKING ISL59481 IRZ TAPE & REEL 13" PACKAGE (Pb-free) PKG. DWG. #
* Pb-free plus anneal (RoHS compliant)
48 Ld Exposed L48.7x7B Pad 7x7 QFN 48 Ld Exposed L48.7x7B Pad 7x7 QFN
Applications
* HDTV/DTV analog inputs * Video projectors * Computer monitors * Set-top boxes * Security video * Broadcast video equipment
ISL59481IRZ-T13 ISL59481 IRZ
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Related Literature
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59481 S1-1, 2 0 0 1 1 X X S0-1, 2 0 1 0 1 X X EN1, EN2 0 0 0 0 1 0 HIZ1, 2 0 0 0 0 X 1 OUTPUT1, 2 IN0 (A, B, C) IN1 (A, B, C) IN2 (A, B, C) IN3 (A, B, C) Power-down High Z
* Application Note AN1235 "ISL59481EVAL1 Evaluation Board User's Guide"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59481 Pinout
ISL59481 (48 LD QFN) TOP VIEW
46 IN3C1 45 IN3B1 44 IN3A1 37 IN1B1 36 IN2A2
0
42 IN2C1
41 IN2B1
40 IN2A1
OUTC1 1 OUTB1 2
+1
38 INIC1
43 GND
39 GND
48 S0-1
47 S1-1
35 GND +1
0
V1- 3 OUTA1 4 V1+ 5 EN1 6 HIZ1 7 IN0C1 8 IN0B1 9 IN0A1 10 GND 11 IN1A1B 12 +1
34 IN1C2 33 IN1B2
0
32 IN1A2 THERMAL PAD 31 GND 30 IN0A2 29 IN0B2 28 IN0C2 27 HIZ2
0 0 0
26 EN2 25 V2+
+1
+1
+1
S1-2 19
S0-2 20
OUTC2 21
OUTB2 22
V2- 23
THERMAL PAD INTERNALLY CONNECTED TO VPAD MUST BE TIED TO V-
Functional Diagram ISL59481
EN0-1 S0-1 EN1-1 S1-1 DECODE1 IN0(A1, B1, C1) IN1(A1, B1, C1) EN2-1 IN2(A1, B1, C1) IN3(A1, B1, C1) EN3-1 AMPLIFIER1 BIAS HIZ1 EN1 EN0-2 S0-2 EN1-2 S1-2 DECODE2 IN0(A2, B2, C2) IN1(A2, B2, C2) EN2-2 IN2(A2, B2, C2) IN3(A2, B2, C2) EN3-2 AMPLIFIER2 BIAS HIZ2 EN2 OUT(A2, B2, C2) OUT(A1, B1, C1)
2
OUTA2 24
IN2B2 13
IN2C2 14
GND 15
IN3A2 16
IN3B2 17
IN3C2 18
FN6208.3 December 22, 2006
ISL59481
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital and Analog Input Current (Note 1) . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL
V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25C, Input Video = 1VP-P and RL = 500 to GND, CL = 5pF unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
+IS Enabled -IS Enabled
+IS Disabled -IS Disabled VOUT IOUT VOS Ib ROUT ROUT RIN ACL or AV IHIZ LOGIC VIH VIL IIH IIL AC GENERAL tS PSRR ISO dG dP BW
Enabled Supply Current Enabled Supply Current Disabled Supply Current Disabled Supply Current Positive and Negative Output Swing Output Current Output Offset Voltage Input Bias Current HIZ Output Resistance Enabled Output Resistance Input Resistance Voltage Gain Output Current in High Impedance state
No load, VIN = 0V, EN1, EN2 Low No load, VIN = 0V, EN1, EN2 Low No load, VIN = 0V, EN1, EN2 High No load, VIN = 0V, EN1, EN2 High VIN = 3.5V, RL = 500 RL = 10 to GND VIN = 0V VIN = 0V HIZ = Logic High HIZ = Logic Low VIN = 3.5V VIN = 1.5V, RL= 500 VOUT = 0V
75 -96 5 -250 3.1 80 -10 -10
92 -92 6.2 -20 3.4 135
100 -68 8
mA mA mA A |V| |mA|
14 -2 1.2 0.1 10 +10
mV A M M
0.98
0.99 1.2
1.02
V/V A
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs) VH = 5V VL = 0V
2 0.8 215 -10 270 -1 320 +10
V V A A
0.1% Settling Time Power Supply Rejection Ratio Channel Isolation Differential Gain Error Differential Phase Error -3dB Bandwidth
RL= 500, CL = 1.5pF, Step = 1V DC, PSRR V+ and V- combined f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.5pF NTC-7, RL = 150, CL = 1.5pF NTC-7, RL = 150, CL = 1.5pF CL = 1.5pF 52
10 56 75 0.02 0.02 500
ns dB dB % MHz
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FN6208.3 December 22, 2006
ISL59481
Electrical Specifications
PARAMETER FBW V1+ = V2+ = +5V, V1- = V2- = -5V, GND = 0V, TA = +25C, Input Video = 1VP-P and RL = 500 to GND, CL = 5pF unless otherwise specified. (Continued) DESCRIPTION 0.1dB Bandwidth 0.1dB Bandwidth SR Slew Rate CL = 1.5pF CL = 4.7pF 25% to 75%, RL = 150, Input Enabled, CL = 1.5pF CONDITIONS MIN TYP 60 120 MAX UNIT MHz MHz V/s
870
SWITCHING CHARACTERISTICS VGLITCH Channel-to-Channel Switching Glitch EN Switching Glitch HIZ Switching Glitch tSW-L-H tSW-H-L tr, tf tpd Channel Switching Time Low to High Channel Switching Time High to Low Rise and Fall Time Propagation Delay VIN = 0V CL = 1.5pF VIN = 0V CL = 1.5pF VIN = 0V CL = 1.5pF 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% to 90% 10% to 10% 20 200 200 18 20 1.1 0.9 mVP-P mVP-P mVP-P ns ns ns ns
Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 1M 10M 100M FREQUENCY (Hz) 1G CL INCLUDES 1.5pF BOARD CAPACITANCE CL=4.7pF CL=2.2pF CL=1.5pF SOURCE POWER=-20dBm CL=16.5pF NORMALIZED GAIN (dB) CL=11.5pF CL=7.3pF CL=6.2pF 5 4 3 2 1 0 -1 -2 -3 -4 -5 1M 10M 100M FREQUENCY (Hz) 1G RL=100 RL=150 RL=500 RL=1k SOURCE POWER=-20dBm
FIGURE 1. GAIN vs FREQUENCY vs CL
0.2 SOURCE 0.1 POWER=-20dBm OUTPUT RESISTANCE () 0.0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1M 10M 100M FREQUENCY (Hz) 1G 0.1 0.1M CL=1.5pF CL=4.7pF 100
FIGURE 2. GAIN vs FREQUENCY vs RL
10
1
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 3. 0.1dB GAIN vs FREQUENCY
FIGURE 4. ROUT vs FREQUENCY
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FN6208.3 December 22, 2006
ISL59481 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
0.8 0.6 0.4 0.2 VOUT (V) 0.0 -0.2 -0.4 -80 -0.6 -0.8 TIME (5ns/DIV) -90 -100 0.1M 1M 10M FREQUENCY (Hz) 100M 1G (dB) RL=500 CL=1.5pF 0 -10 -20 -30 -40 -50 -60 -70 OFF ISOLATION INPUT X TO OUTPUT X INPUT X TO OUTPUT Y CROSSTALK
(Continued)
FIGURE 5. TRANSIENT RESPONSE
FIGURE 6. CROSSTALK AND OFF ISOLATION
20 10 0 -10 PSRR (dB) -20 -30 -40 -50 -60 -70 -80 0.3M 1M 10M FREQUENCY (Hz) 100M 1G 20mV/DIV 0 VOUT A, B, C 20ns/DIV 0 PSRR (V-) PSRR (V+) 1V/DIV S0, S1 50 TERM. VIN = 0V
FIGURE 7. PSRR CHANNELS A, B, C
FIGURE 8. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
S0, S1 50 TERM. 1V/DIV
VIN = 1V
ENABLE 50 TERM. 1V/DIV
VIN = 0V
0 100mV/DIV
0
0.5V/DIV
VOUT A, B, C 0
0
VOUT A, B, C 20ns/DIV
20ns/DIV
FIGURE 9. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V
FIGURE 10. ENABLE SWITCHING GLITCH VIN = 0V
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FN6208.3 December 22, 2006
ISL59481 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = +25C, unless otherwise specified.
ENABLE 50 TERM. 1V/DIV 1V/DIV VIN = 1V HIZ 50 TERM.
(Continued)
VIN = 0V
0 200mv/DIV
0
1V/DIV
0 VOUT A, B, C 10ns/DIV
0
VOUT A, B, C
20ns/DIV
FIGURE 11. ENABLE TRANSIENT RESPONSE VIN = 1V
FIGURE 12. HIZ SWITCHING GLITCH VIN = 0V
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 HIZ 50 TERM. 1V/DIV VIN=1V POWER DISSIPATION (W) 6 5 4.34W 4 3 2 1 0 0 10ns/DIV 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QFN48 JA =23C/W
0
1V/DIV
VOUT A, B, C 0
FIGURE 13. HIZ TRANSIENT RESPONSE VIN = 1V
FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
6
FN6208.3 December 22, 2006
ISL59481 Pin Description
ISL59481 (48 LD QFN) 1 2 3, 23 4 5, 25 6 26 7 27 8 9 10 11 12 13 14 15 16 17 18 19, 47 20, 48 21 22 24 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 PIN NAME OUTC1 OUTB1 V1-, V2OUTA1 V1+, V2+ EN1 EN2 HIZ1 HIZ2 IN0C1 IN0B1 IN0A1 GND IN1A1 IN2B2 IN2C2 GND IN3A2 IN3B2 IN3C2 S1-2, S1-1 S0-2, S0-1 OUTC2 OUTB2 OUTA2 IN0C2 IN0B2 IN0A2 GND IN1A2 IN1B2 IN1C2 GND IN2A2 IN1B1 IN1C1 GND IN2A1 IN2B1 IN2C1 GND IN3A1 IN3B1 IN3C1 Circuit 1 Circuit 1 Circuit 1 Circuit 4A Circuit 1 Circuit 1 Circuit 1 Circuit 4B Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 2 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 1 Circuit 4B Circuit 1 Circuit 1 Circuit 1 Circuit 4B Circuit 1 Circuit 1 Circuit 1 Circuit 4A Circuit 1 Circuit 1 Circuit 1 Circuit 4A Circuit 1 Circuit 1 Circuit 1 Circuit 2 EQUIVALENT CIRCUIT Circuit 3 Circuit 3 Circuit 4A Circuit 3 Circuit 4A Circuit 2 Output of amplifier C1 Output of amplifier B1 Negative power supply #1 and #2 Output of amplifier A1 Positive Power Supply #1 and #2 Device enable (active low) with internal pull-down resistor. A logic High puts device into power-down mode leaving the logic circuitry active. This state is not recommended for logic control where more than one MUX-amp share the same video output line. Output disable (active high) with internal pull-down resistor. A logic high puts the output in a high impedance state. Use this state when more than one MUX-amp share the same video output line. Channel 0 input for amplifier C1 Channel 0 input for amplifier B1 Channel 0 input for amplifier A1 Ground pin for amplifier A1 Channel 1 input for amplifier A1 Channel 2 input for amplifier B2 Channel 2 input for amplifier C2 Ground pin for amplifier C2 Channel 3 input for amplifier A2 Channel 3 input for amplifier B2 Channel 3 input for amplifier C2 Channel select pin MSB (binary logic code) for amplifiers A2, B2, C2 (S1-2) and A1, B1, C1 (S1-1) Channel select pin LSB (binary logic code) for amplifiers A2, B2, C2 (S0-2) and A1, B1, C1 (S0-1) Output of amplifier C2 Output of amplifier B2 Output of amplifier A2 Channel 0 input for amplifier A2 Channel 0 input for amplifier B2 Channel 0 input for amplifier C2 Ground pin for amplifier C2 Channel 1 input for amplifier A2 Channel 1 input for amplifier B2 Channel 1 input for amplifier C2 Ground pin for amplifier B2 Channel 2 input for amplifier A2 Channel 1 input for amplifier B1 Channel 1 input for amplifier C1 Ground pin for amplifier B1 Channel 2 input for amplifier A1 Channel 2 input for amplifier B1 Channel 2 input for amplifier C1 Ground pin for amplifier C1 Channel 3 input for amplifier A1 Channel 3 input for amplifier B1 Channel 3 input for amplifier C1 DESCRIPTION
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FN6208.3 December 22, 2006
ISL59481 Pin Equivalent Circuits
V+ IN LOGIC PIN 21k 33k V+ 1.2V V+ GND VCIRCUIT 2 V2+ GNDA2
CAPACITIVELY COUPLED ESD CLAMP CAPACITIVELY COUPLED ESD CLAMP
V+ OUT V-
CIRCUIT 1
V1+ GNDA1 GNDB1 GNDC1 V1CIRCUIT 4A
CIRCUIT 3
SUBSTRATE 1 V1~1M
SUBSTRATE 2 V2~1M
GNDB2 GNDC2 V2CIRCUIT 4B
THERMAL HEAT SINK PAD
AC Test Circuits
ISL59481 VIN 50 or 75 CL 5pF RL 500
Application Information
General
The ISL59481 is ideal as the matrix element of high performance switchers and routers. Key features include high impedance buffered analog inputs and excellent AC performance at output loads down to 150 for video cabledriving. The unity-gain current feedback output amplifiers are stable operating into capacitive loads and bandwidth is optimized with a load of 5pF in parallel with a 500. Total output capacitance can be split between the PCB capacitance and an external load capacitor.
FIGURE 15A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
ISL59481 VIN 50 or 75 CL 5pF RS 475 50 or 75
TEST EQUIPMENT 50 or 75
Ground Connections
For the best isolation and crosstalk rejection, all GND pins must connect to the GND plane.
Power-up Considerations
FIGURE 15B. TEST CIRCUIT FOR MEASURING WITH 50 OR 75 INPUT TERMINATED EQUIPMENT
ISL59481 VIN 50 or 75 CL 5pF RS 50 or 75
TEST EQUIPMENT 50 or 75
The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT-triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 16) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. One Schottky can be used to protect both V+ power supply pins, and a second for the protection of both V- pins.
FIGURE 15C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500 WILL BE DEGRADED. FIGURE 15. TEST CIRCUITS
Figure 15A illustrates the optimum output load for testing AC performance. Figure 15B illustrates the optimum output load when connecting to 50 input terminated equipment.
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FN6208.3 December 22, 2006
ISL59481
V+ SUPPLY SCHOTTKY PROTECTION LOGIC POWER GND SIGNAL DE-COUPLING CAPS V- SUPPLY S0 GND IN0 IN1 VVVV+ VVV+ V+ OUT V+ V+ LOGIC CONTROL EXTERNAL CIRCUITS
FIGURE 16. SCHOTTKY PROTECTION CIRCUIT
If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+.
PC Board Layout
The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless controlled impedance (50 or 75) strip lines or microstrips are used. * Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * A minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
HIZ State
Each internal 4:1 triple MUX-amp has a three-state output control pin (HIZ1 and HIZ2). Each has an internal pull-down resistor to set the output to the enabled state with no connection to the HIZ pin. The HIZ state is established within approximately 15ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4M with approximately 1.5pF in parallel with a 10A bias current from the output. When more than one MUX shares a common output, the high impedance state loading effect is minimized over the maximum output voltage swing and maintains its high Z even in the presence of high slew rates. The supply current during this state is the same as the active state.
EN and Power-down States
The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 80ns, if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three amplifiers off. The output presents a high impedance to the output pin, however, there is a risk that the disabled amplifier output can be back-driven at signal voltage levels exceeding ~2VP-P. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited power-down output impedance.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. 9
FN6208.3 December 22, 2006
ISL59481
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V1- and V2- supply pins through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND as this could result in large back biased currents flowing between GND and the V- pins. Maximum AC performance is achieved if the thermal pad is attached to a dedicated decoupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible, an isolated thermal pad on another layer should be used. Pad area requirements should be evaluated on a case by case basis. amp2 in a similar fashion. The individual control for each 4:1 triple MUX enables external connections to configure the device for different MUX applications.
8:1 RGB Video MUX
For a triple input RGB 8:1 MUX (Figure 17), the RGB amplifier outputs of MUX-amp1 are parallel-connected to the RGB amplifier outputs of MUX-amp2 to produce the single RGB video output. Input channels CH0 to CH3 are assigned to MUX-amp1, and channels CH4 through CH7 are assigned to MUX-amp2. Channels CH0 through CH3 are selected by setting HIZ1 low, HIZ2 high (enables MUX-amp1 and threestates MUX-amp2), and the appropriate channel select logic to S0-1, S1-1. Reversing the logic inputs of HIZ1, HIZ2 switches from MUX-amp1 to MUX-amp2 enables the selection of channels CH4 through CH7. The channel select inputs are parallel connected (S0-1 to S0-2) and (S1-1 to S1-2) to form two logic controls S0, S1. A single S2 control is split into complimentary logic inputs for HIZ1 and HIZ2 to produce a chip select function for the MSB. The logic control truth table is shown in Figure 17.
MUX Application Circuits
Each of the two 4:1 triple MUX amplifiers have their own binary-coded, TTL compatible channel select logic inputs (S0-1, 2, and S1-1, 2). All three amplifiers are switched simultaneously from their respective inputs with S0-1 S1-1 controlling MUX-amp1, and S0-2, S1-2 controlling MUXamp2. The HIZ control inputs (HIZ1, HIZ2) and device enable control inputs (EN1 and EN2) control MUX-amp1 and MUX-
ISL59481
1/3 MUX-AMP1 CH0 CH1 CH2 CH3 CH0A - CH7A CHANNELS B & C NOT SHOWN CH4 CH5 CH6 CH7 S0 CHANNEL SELECT LOGIC INPUTS S1 S2 IN0A1 IN1A1 IN2A1 IN3A1 S0-1 S1-1 HIZ1 IN0A2 IN1A2 IN2A2 IN3A2 S0-2 S1-2 HIZ2
CONTROL LOGIC CONTROL LOGIC
+1
OUTA1
CHANNEL SELECT TRUTH TABLE 8:1 VIDEO MUX
S2 0 OUTA 0 0 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 OUTA, B, C CH0A, B, C CH1A, B, C CH2A, B, C CH3A, B, C CH4A, B, C CH5A,B,C CH6A, B, C CH7A, B, C
1/3 MUX-AMP2 OUTA2
0 1 1 1 1
+1
FIGURE 17. APPLICATION CIRCUIT FOR 8:1 RGB VIDEO MUX
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FN6208.3 December 22, 2006
ISL59481
4:1 RGB Differential Video MUX
Connecting the channel select pins in parallel (S0-1 to S0-2 and S1-1 to S1-2) converts the 8 individual RGB video inputs into 4 differential RGB input pairs. The amplifier RGB outputs are similarly paired resulting in a fully differential 4:1 RGB MUX amp shown in Figure 18. Connecting HIZ1 and HIZ2 to +5V disables the 4:1 differential MUX, and enables the connection of additional differential-connected MUX amplifiers to the same outputs, thus allowing input expansion to 8:1 or more.
ISL59481
1/3 MUX-AMP1 CH0 + IN0A1 IN1A1 IN2A1 IN3A1 + S0-1 S1-1 HIZ1 CH2 + IN0A2 IN1A2 IN2A2 CH1 + +1 OUTA2 1/3 MUX-AMP2
CONTROL LOGIC
-
+1
OUTA1
CHANNEL SELECT TRUTH TABLE 4:1 DIFFERENTIAL VIDEO MUX
S1 + OUTA 0 0 1 1 S0 0 1 0 1 OUTA, B, C CH0A, B, C CH1A, B, C CH2A, B, C CH3A, B, C
CH0A - CH3A CHANNELS B & C NOT SHOWN
CH1
-
-
-
-
IN3A2 S0-2 S1-2 HIZ HIZ2
CONTROL LOGIC
CHANNEL SELECT LOGIC INPUTS
S0 S1
FIGURE 18. APPLICATION CIRCUIT FOR 4:1 RGB DIFFERENTIAL VIDEO MUX
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6208.3 December 22, 2006
ISL59481
Package Outline Drawing
L48.7x7B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 12/06
4X 5.5 7.00 A B 6 PIN 1 INDEX AREA 37 36 44X 0.50 48 1 6 PIN #1 INDEX AREA
7.00
3.70
25 (4X) 0.15 24 TOP VIEW 48X 0 . 40 13
12
0.10 M C A B 4 0.25
BOTTOM VIEW
SEE DETAIL "X" 0.10 C BASE PLANE C
( 6 . 80 TYP ) ( 3.70 )
0 . 85 0 . 1
SIDE VIEW ( 44X 0 . 5 )
SEATING PLANE 0.08 C
C ( 48X 0 . 25 ) ( 48X 0 . 60 ) TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
12
FN6208.3 December 22, 2006

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